1. Field of the Invention
The present invention relates to technology of an interposer for a chip size package which is interposed between a semiconductor device and a circuit board for electric connection therebetween when the semiconductor device is packaged on the circuit board.
The present application is based on Japanese Patent Applications No. Hei. 11-96918 and 11-224221, which is incorporated herein by reference.
2. Description of the Related Art
Generally, a large number of semiconductor devices such as ICs are formed on a wafer, and separated into individual chips which are connected to several kinds of circuit boards. Further large-scale integration of an IC increases the number of electrodes formed on a single chip so that the shape of each electrode and the array pattern is fine and provide a narrow pitch. In the field of packaging technology, a method (e.g. flip-chip bonding) has been proposed which does not use wire bridging between a chip and a circuit board, but use correlative connecting between the electrode position of the chip and conductor portion of the circuit board. In order to satisfy the requirement of miniaturization, a bare chip packaging in which the chip is packaged in an naked state has been proposed.
In recent years, in accordance with the above requirement, a xe2x80x9cchip size packagexe2x80x9d (CSP) has been proposed which packages the chip on a circuit board with its size being maintained to occupy a much smaller area than a conventional package does. The CSP achieves the packaging of the chip size by interposing a flexible circuit board (called xe2x80x9cinterposerxe2x80x9d) 20 equipped with a contact between a chip 30 and an external circuit board 40 for their interconnection as shown in FIG. 7A. The circuit board may be various kinds such as a circuit board for packaging or a general circuit board on which a large number of elements are also packaged.
As shown in FIG. 7A, the interposer 20 includes a circuit pattern 22 within an insulating substrate 21 (which actually has a laminated structure) which has a size approximately equal to or slightly larger than the chip 30. The interposer 20 has also a contact 23 in the insulating substrate 21 on the side of the chip 30 at the position which individually corresponds to the electrode pad (not shown) of the chip. The interposer has also a contact 24 in the insulating substrate 21 on the side of the circuit board at the position which corresponds to the pad of the circuit formed on the circuit board. These contacts 23 and 24 are formed in various manners of a bump, a flat form in flush with the substrate surface, etc. These large number of contacts 23 and 24 lead to the internal circuit pattern 22. In this way, the individual electrodes of the chip is connected to the circuit 41 of the circuit board 40 through the contact 23, circuit pattern 22 and contact 24 of the interposer 20.
However, the contacts formed in the conventional interposer have greatly different heights with respect to the surface of the insulating substrate 21. Now, the xe2x80x9cheightxe2x80x9d refers to the height of the contact which is not only projected from the substrate surface but also dented therefrom. Because of such height difference, some of the contacts cannot be in contact with the electrodes formed on the rigid chip 30. This gives rise to a problem in reliability of connection.
In the example shown in FIG. 7B, a contact 23b, which is located between the surrounding contacts 23a and 23c and has a projecting height lower than them by a distance y, cannot be brought into contact with the chip 30. If the projecting height of the pertinent contact is slightly lower than that of the surrounding contacts, it is apparently in contact with the chip. However, its contact area is smaller by the degree of reduction of a crushing margin when it is brought into contact. This cannot provide good reliability in connection.
Since the interposer 20 is interposed between the chip 30 and the circuit board 40, the above problem in connection between the interposer 20 and the chip 30 occurs also in connection between the interposer 20 and the circuit board 40. Specifically, as understood by replacing the chip 30 by the circuit board 40, the contact which is lower by y in its projecting height than the surrounding contacts cannot be brought into contact with the conductor portion of the circuit board.
A primary object of the present invention is to solve the above problems occurring in connection between the interposer and the chip and between the interposer and the circuit board.
Another object of the present invention is to provide a method of manufacturing an interposer for CSP which can reduce a difference in the height among contacts with respect to a surface of an insulating substrate.
Still another object of the present invention is to provide a preferable interposer for CSP and its intermediate member which can be obtained by the above manufacturing method.
The method for manufacturing an interposer for CSP according to the present invention, interposer itself and its intermediate body have the following aspects or features.
(1) A method for manufacturing an interposer for a chip size package, comprising:
a first step of forming a first insulating layer on a substrate which is made of metal and usable as a cathode for electroplating;
a second step of forming a first opening at a position of the insulating layer corresponding to a conductor portion of an object for connection so that a surface of the substrate is exposed to an inner bottom of the opening;
a third step of filling the first opening with metal by electroplating using the substrate as a cathode, thereby forming a conductive path in the first opening;
a fourth step of forming a circuit pattern in contact with the conductive path on the first insulating layer; and
a fifth step of removing the substrate partially or entirely to expose the first insulating layer inclusive of an end surface of the conductive path.
(2) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is an electrode of a chip.
(3) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is a conductor portion of a circuit board.
(4) A method for manufacturing an interposer according to the aspect (1) or (2), wherein the first insulating layer is made of photosensitive and thermal melting type adhesive resin.
(5) A method for manufacturing an interposer according to the aspect (1), further, after the fourth step, comprising the step of:
forming a second insulating layer so as to cover the circuit pattern and forming a second opening from which the circuit pattern is exposed.
(6) A method for manufacturing an interposer according to the aspect (1), wherein the conductor portion of the object for connection is a conductor portion of a circuit board, further comprising, after the fourth step, the step of:
forming a second insulating layer so as to cover the circuit pattern and forming a second opening exposing the circuit pattern at a position of an electrode of a chip which is the object for connection, and filling the second opening with metal.
(7) A method for manufacturing an interposer according to the aspect (6), wherein the first insulating layer is made of photosensitive resin, and the second insulating layer is made of photosensitive and thermal melting type adhesive resin.
(8) A method for manufacturing an interposer according to the aspect (1), wherein in the fifth step, the substrate for a cathode is removed to be left as a frame for supporting the interposer on its periphery.
(9) A method for manufacturing an interposer according to the aspect (1), wherein the substrate has an outer size enough to arrange a plurality of interposers for a chip size package, and the plurality of interposers which are collected on the substrate in a state where they can be separated in individual components after they have experienced the first to fifth steps.
(10) A method for manufacturing an interposer according to the aspect (9), wherein in the fifth step, the substrate is removed to be left as frames which surround and support the plurality of interposers individually, and/or to be left as a frame which inclusively surrounds the plurality of interposers.
(11) An interposer for a chip size package having a metallic frame on its outer periphery.
(12) An intermediate body of an interposer for a chip size package wherein a sheet-like collection of a plurality of interposers for a chip size package are provided, and a metallic frame which inclusively surrounds all the plurality of interposers is provided on the outer periphery of the collection.
(13) An intermediate body of an interposer for a chip size package wherein a sheet-like collection of a plurality of interposers for a chip size package are provided, and each of metallic frames is provided on the periphery of each the individual interposers.
In a conventional typical process of making a contact, as understood from the contacts on a chip side shown in FIG. 7B, openings are made in an insulating substrate 21 and circuit patterns 22a-22c are exposed to inner bottoms of the openings. The respective openings are filled with highly-conductive metal precipitated in each of the openings by electroplating using each circuit pattern as a cathode, thereby providing contacts 23a-23c on the top. However, the electroplating theoretically produces variations in the current density, and hence different thicknesses of the plated films at different positions. Namely, the heights of the contacts 23a-23c are different for the respective openings because the amount of precipitation of material varies for each opening.
Unlike the above conventional process, in accordance with the present invention, as shown in FIG. 1A, a substrate 1 for a cathode (hereinafter referred to as xe2x80x9ccathode substratexe2x80x9d) which will be removed finally is prepared. As shown in FIG. 1B, an opening 3 is filled with a conductive path 4 using the cathode substract. As shown in FIOG. 1C, the cathode is removed to expose the end surface 4a of the conductive path so that it is used as a contact.
In short, the contact surface in the conventional process is a final portion grown from a cathode plate (circuit pattern) to a far substrate surface (reference plane) through the conductive path. On the other hand, the contact surface in the present invention is an initial portion precipitated to the surface of the cathode substrate (plane abutting on the reference plane). Therefore, addition of a thin film of Au on the contact surface does not produce a great variation in the heights of the contacts.
Now it is assumed that the opening provided in a polyimide substrate having a thickness of 20 xcexcm is filled with Cu so that the end surface of Cu is used as a contact. In this case, there is the following variation of in numerical values of the contact heights.
Where it is desired that the contact height is 0 xcexcm (i.e. the contact is flush with the substrate surface), in accordance with the present invention, as shown in FIG. 6A, the substrate surface appearing by removing the cathode substrate is flush with the contact surface, the variation thereof is theoretically xc2x10. In contrast, in the conventional process, as shown in FIG. 6C, the contact height is a result when the metal has been grown to the height of 20 xcexcm from the circuit pattern. Thus, the variation is xc2x1 about 3 xcexcm. The shape of the contact surface is not flat but convex as it is in the precipitated state.
Where it is desired that the contact height is 10 xcexcm, in accordance with the present invention, as shown in FIG. 6B, Cu is further grown by 10 xcexcm from the contact surface acquired in FIG. 6A. The variation is about xc2x12 xcexcm. In contrast, in the conventional process, as shown in FIG. 6D, the contact height is a result when the metal has been grown to the height of 30 xcexcm from the circuit pattern. Thus, the variation is xc2x1 about 5 xcexcm.
To reduce the variation in the contact height is useful for both chip side and circuit board side. For this reason, from the standpoint of reliability of connection, whether the contact with less variation, which appears by removing the cathode substrate, should be adopted on the chip side or the circuit board side may be determined according to the requirement of a product.
On the other hand, in accordance with the present invention, it is noticed that the property required for the insulating layer on the chip side may be different from that on the circuit board side. It has been found that the substrate surface appearing when the cathode substrate is removed and its contact may be preferably adopted for the circuit board side. The details thereof will be explained below.
From the standpoint of a method of making an opening, both insulating layers are preferably made of photosensitive resin, particularly, photosensitive polyimide which is xe2x80x9cpolyimidedxe2x80x9d by heating for curing. However, in the insulating layer on the chip side, which is further conditioned on chip packaging, the insulating layer preferably serves as an adhesive layer as described later. Therefore, the insulating layer is made preferably of photosensitive and thermally-melting adhesive resin. On the other hand, the material of the insulating layer on the circuit board side may be only photosensitive.
In many cases, some photosensitive resin materials (resin on the circuit board side) exhibiting excellent characteristics have a curing temperature exceeding the appropriate curing temperature of the photosensitive and thermally-melting adhesive resin (resin on the chip side). Particularly, where [ODPA: (MAPB, APDS)] (described later) is used as the resin on the chip side and [(ODPA, BPDA):(PPD, DDE) (described later) is used as the resin on the circuit board side, the appropriate curing temperature of the former is 300xc2x0 C. whereas that of the latter is 400xc2x0 C., which results in a large difference of 100xc2x0 C. therebetween. In the case where there is such a large difference in the curing temperature, it is preferable to form insulating layers in the order of a higher curing temperature. Namely, the preferred order of making the insulating layers is that as shown in FIGS. 5A-5F, the first insulating layer initially formed on the cathode substrate 1 is used as an insulating layer having a higher curing temperature on the circuit board side, and the second insulating layer 6B formed thereafter is used as an insulating layer having a lower curing temperature on the chip side.
In the above processing order, the first insulating layer can be cured sufficiently at 400xc2x0 C. (xe2x80x9cfull curingxe2x80x9d) without considering the affect on the environment so that it can sufficiently exhibit the inherent property. Even when the second insulating layer is cured at 300xc2x0 C., the first insulating layer will not be damaged because it has experienced the heating treatment at 400xc2x0 C. Thus, both first insulating layer and second insulating layer can exhibit their inherent properties.
When there is a large difference in the curing temperature, if the first insulating layer is formed using the resin having a lower curing temperature, it will be damaged by the curing or sputtering of the second insulating layer at a high temperature. Thus, the first insulating layer suffers from quality deterioration that its property as thermally-melting adhesive resin (fluidity of the resin) is lost, the entire layer becomes fragile and the adhesive force is lowered. In this case, taking the quality of the first insulating layer into consideration, if the second insulating layer is cured at the lower temperature, it will not be subjected to the curing at the appropriate temperature. Thus, the second insulating layer will be located in an xe2x80x9cunder-curingxe2x80x9d state where the polyamide acid will not be changed into polyimide. The xe2x80x9cunder-curingxe2x80x9d state refers to the state where the curing condition is not sufficiently satisfied, i.e. the insulating layer cannot exhibit the inherent resin properties in terms of its mechanical strength, heat-resistance, medicine resistance, etc. This greatly deteriorates the reliability of the interposer structure itself.
The features defined in the aspects (11) to (13) of the present invention are an interposer, or intermediate bodies obtained by the process according to the present invention, in which the cathode substrate is not entirely removed but left as a metallic frame on the periphery. These aspects suppress the variation in the contact heights and provide the following advantages.
In a conventional technique of packaging of an interposer on a chip, a plurality of interposers are collected in a matrix on a sheet and the chips are mounted mass-productively on the sheet and cut into individual packaging bodies. Each interposer is a very thin flexible circuit board as a whole. The sheet composed of a collection of these interposers provides poor handling with no stiffness. In order to set such a sheet in a packaging machine, a dedicated metallic jig has been conventionally used. The metallic jig has a frame structure which can support the outer periphery of the sheet, generally a metallic frame plate having a thickness of 50 xcexcm-500 xcexcm. Guide pins for positioning are provided on the respective sides of the frame of the metallic jig. These pins are fit into holes for positioning formed on the outer periphery of the sheet so that the sheet is secured to fixed positions of the metallic jig. Since the outer periphery of the sheet is supported by the metallic jig, handling of the sheet can be improved and its positioning on the packaging machine can be made properly. On the other hand, in accordance with the present invention, as shown in FIG. 2A as an intermediate body defined in the above aspect (12), the cathode substrate 1 is not completely removed but left as a frame serving as a metallic jig. Unlike the conventional packaging process, this feature makes it unnecessary to prepare a metallic jig for an interposer and to set the interposer sheet in the metallic jig. Incidentally, the frame portion will be removed when the sheet is cut.
In order to handle a chip having a large number of electrodes, it is necessary to make the outer size of the interposer larger than that of the chip thereby to extend the circuit pattern outwardly of the chip. To this end, for example, as shown in FIG. 3, the region where the opening 7 filled with a solder bump 8 is formed on a circuit board side is greatly extended out. However, the portion of the interposer extended out from chip is thin and flexible so that it is difficult to connect the interposer to an external circuit and handle it smoothly. In order to formulate the interposer in such a structure, in accordance with the present invention, as shown in FIGS. 4F and 2B, the cathode substrate 1 is not completely removed, but only the regions in which the individual chips are fit are etched so that the substrate is left as frames each of which supports the outer periphery of each interposer. Such a structure corresponds to the interposer defined in the aspect (11) and its intermediate body defined in the aspect (13). In these aspects, in the case of the interposer having a larger size than the chip size, the portion of the interposer extended out from the chip can be given stiffness. This makes it unnecessary to provide a reinforcement plate redundantly.
The above and other objects and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.